Maven Silicon invites Students of Government Engineering College, Bharuch for Free VLSI Webinar on RTL Design and Functional Verification. Interested students can register through below link. Students must register twice with two different links.
Register for Webinar for college record
second link for registration
Webinar Topic: RTL Design and Functional Verification
The Webinar aims at giving an overview of RTL Design and Functional Verification. This webinar will provide the participants an invaluable resource for those who are trying to gain insight about the current needs in the VLSI industry with Key Sessions delivered by Industry Veteran Mr. Sivakumar PR- Founder and CEO of Maven Silicon .
With the minimum requirement of a Projector, speakers & a laptopwith Windows 7 & above with internet connection(5 MBPS dedicated bandwidth), you will be able to host the event in your college.
Highlights of the Webinar:
1. Knowledge sharing by veteran trainer Mr. P R Sivakumar (CEO , Maven Silicon) with the experience of 20+ years in VLSI industry.
2. E-Certificate for the participation
Who can attend?
- Final Year Students of B.Tech/B.E. from ECE, EEE,TE, Instrumentation
- Students of ME/MTech/MS in Electronics, Embedded, VLSI / MSc Electronics
Agenda:
- VLSI Design - Overview
- IPs, Chips and SoCs
- VLSI Design Flow – Frontend Vs Backend
- RTL Design – HDLs
- Verilog Vs VHDL
- Overview of Verilog
- Functional Verification
- SV and UVM based Testbenches
- Code and Functional coverage
- Indian Semiconductor Industry
- VLSI Companies
- Products and road maps
- Job Opportunities
- VLSI Training
- VLSI Finishing school
- Maven Silicon overview
- How to start?
- Q&A Session
Important Note :
- Kindly share the attached spreadsheet with student's details, who are attending the Webinar. Being a Free Webinar, we have limited slots , It would be highly appreciated, if you provide the list at the earliest.
- For any query , Please call us on +91 9108490555 | +91 7338454291.
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